Comprehensive Study Guide for NEC License Exam - Computer Engineering

4. Computer Organization and Embedded System (ACtE04)

Introduction

The Nepal Engineering Council (NEC) License Exam is a mandatory requirement for Computer Engineering graduates in Nepal to register as professional engineers. The section 4. Computer Organization and Embedded System (ACtE04) tests knowledge of computer architecture, memory systems, input-output mechanisms, embedded systems, real-time operating systems, and hardware description languages. These topics are critical for designing efficient computing systems and embedded applications. This comprehensive note covers all subtopics (4.1 to 4.6) with detailed explanations, code examples (where applicable), diagram names, and exam-focused strategies to ensure students can rely on it for thorough preparation. The exam consists of 100 multiple-choice questions (MCQs), with 10 marks allocated to this section, requiring a 50% passing threshold and no negative marking.

The syllabus includes:

• 4.1 Control and central processing units (ACtE0401)
• 4.2 Computer arithmetic and memory system (ACtE0402)
• 4.3 Input-Output organization and multiprocessor (ACtE0403)
• 4.4 Hardware-Software design issues on embedded system (ACtE0404)
• 4.5 Real-Time operating and control system (ACtE0405)
• 4.6 Hardware descripts language and IC technology (ACtE0406)

4.1 Control and Central Processing Units (ACtE0401)

Key Concepts

Control Memory: Stores microinstructions for executing instructions, typically in ROM or RAM within the control unit.

Addressing Sequencing: Determines the order of microinstructions (e.g., sequential, conditional branching).

Computer Configuration: Defines CPU, memory, and I/O organization (e.g., von Neumann vs. Harvard architecture).

Microinstruction Format: Fields include operation code, source/destination registers, and control signals.

Design of Control Unit:

• Hardwired: Fixed logic, faster but inflexible.
• Microprogrammed: Uses microinstructions, flexible but slower.

CPU Structure and Function: Components include ALU, registers (PC, IR, MAR, MBR), and control unit.

Arithmetic and Logic Unit (ALU): Performs arithmetic (add, subtract) and logical (AND, OR) operations.

Instruction Formats: Types include zero, one, two, or three-address instructions (e.g., ADD R1, R2, R3).

Addressing Modes: Immediate, direct, indirect, register, indexed, base-register.

Data Transfer and Manipulation: Instructions for moving data (e.g., MOV) and operations (e.g., ADD, AND).

RISC vs. CISC:

• RISC: Reduced Instruction Set Computer, simple instructions, fixed length (e.g., ARM).
• CISC: Complex Instruction Set Computer, complex instructions, variable length (e.g., x86).

Pipelining: Overlaps instruction fetch, decode, and execute stages to improve throughput.

Parallel Processing: Multiple instructions executed simultaneously (e.g., SIMD, MIMD).

Diagram Names

• CPU Block Diagram
• Instruction Pipeline Diagram
• Control Unit Design Diagram

Common MCQ Areas

• Differences between RISC and CISC architectures.
• Addressing modes and their applications.
• Pipelining stages and hazards.

Practice Tips

• Study “Computer Organization and Architecture” by William Stallings for CPU and control unit concepts.
• Practice identifying addressing modes in instructions (e.g., immediate vs. indirect).
• Draw pipeline stages for a 5-stage processor and calculate throughput.
• Compare RISC and CISC features using examples like ARM and x86.

Sample MCQs

1. Which addressing mode uses the instruction itself as the operand?

   • a) Direct
   • b) Immediate
   • c) Indirect
   • d) Register
   • Answer: b) Immediate.

2. RISC processors typically have:

   • a) Variable-length instructions
   • b) Complex instructions
   • c) Fixed-length instructions
   • d) Fewer registers
   • Answer: c) Fixed-length instructions.

4.2 Computer Arithmetic and Memory System (ACtE0402)

Key Concepts

Arithmetic and Logical Operations: Addition, subtraction, AND, OR, XOR, shift (e.g., A << 2).

Memory Hierarchy: Registers (fastest), cache, main memory (RAM), secondary storage (HDD/SSD).

Internal Memory: RAM (volatile, SRAM/DRAM), ROM (non-volatile, PROM/EPROM).

External Memory: HDD, SSD, USB drives, optical disks.

Cache Memory Principles: Improves access speed by storing frequently used data.

Elements of Cache Design:

• Cache Size: Small (e.g., 32 KB to 1 MB) for speed.
• Mapping Function: Direct, associative, set-associative.
• Replacement Algorithm: LRU (Least Recently Used), FIFO, Random.
• Write Policy: Write-through, write-back.
• Number of Caches: L1 (on-chip), L2, L3 (shared).

Memory Write Ability and Storage Permanence: Volatile (RAM) vs. non-volatile (ROM, flash).

Composing Memory: Combining SRAM, DRAM, and flash for cost-performance balance.

Diagram Names

• Memory Hierarchy Diagram
• Cache Mapping Diagram
• ALU Operation Diagram

Common MCQ Areas

• Cache mapping techniques and replacement algorithms.
• Memory hierarchy characteristics.
• Arithmetic operations and their hardware implementation.

Practice Tips

• Study “Computer Organization and Architecture” by William Stallings for memory systems.
• Practice cache hit/miss calculations for direct and set-associative mapping.
• Implement binary addition and shift operations manually.
• Compare volatile and non-volatile memory types with examples.

Sample MCQs

1. Which cache mapping allows any block to map to any cache line?

   • a) Direct
   • b) Associative
   • c) Set-associative
   • d) None
   • Answer: b) Associative.

2. Write-back cache policy updates:

   • a) Main memory immediately
   • b) Cache only until eviction
   • c) Both simultaneously
   • d) None
   • Answer: b) Cache only until eviction.

4.3 Input-Output Organization and Multiprocessor (ACtE0403)

Key Concepts

Peripheral Devices: Keyboard, mouse, display, printers, scanners.

I/O Modules: Interface between CPU and peripherals, handling data buffering and control signals.

Input-Output Interface: Ports, buses (e.g., USB, PCIe), and protocols.

Modes of Transfer:

• Programmed I/O: CPU handles transfer, slow.
• Interrupt-Driven I/O: CPU notified on completion.
• DMA: Direct Memory Access, bypasses CPU.

Direct Memory Access (DMA): Transfers data between memory and I/O using a DMA controller (e.g., 8237).

Characteristics of Multiprocessors: Multiple CPUs sharing memory, improving performance.

Interconnection Structure: Bus, crossbar, multistage switch.

Inter-processor Communication: Shared memory or message passing.

Synchronization: Ensures correct data access (e.g., semaphores, locks).

Diagram Names

• I/O Module Block Diagram
• DMA Transfer Diagram
• Multiprocessor Interconnection Diagram

Common MCQ Areas

• Differences between programmed I/O, interrupt-driven I/O, and DMA.
• Multiprocessor interconnection types.
• Synchronization mechanisms in multiprocessors.

Practice Tips

• Study “Computer Organization and Architecture” by William Stallings for I/O and multiprocessors.
• Compare I/O transfer modes with examples (e.g., keyboard vs. disk).
• Analyze DMA operation steps and calculate transfer time.
• Study bus and crossbar interconnection trade-offs.

Sample MCQs

1. DMA is used to:

   • a) Increase CPU load
   • b) Transfer data without CPU
   • c) Handle interrupts
   • d) Manage cache
   • Answer: b) Transfer data without CPU.

2. Which interconnection structure allows multiple simultaneous connections?

   • a) Bus
   • b) Crossbar
   • c) Single-stage
   • d) None
   • Answer: b) Crossbar.

4.4 Hardware-Software Design Issues on Embedded System (ACtE0404)

Key Concepts

Embedded Systems Overview: Specialized systems with dedicated functions (e.g., washing machines, automotive controllers).

Classification: Real-time (hard/soft), networked, standalone.

Custom Single-Purpose Processor Design: Tailored hardware for specific tasks, optimized for power and performance.

Optimizing Custom Processors: Minimize power, size, and cost while meeting performance needs.

Basic Architecture: Microcontroller, memory, I/O ports, timers.

Operation and Programmer’s View: Registers, instruction set, memory map.

Development Environment: Cross-compilers, debuggers, emulators.

Application-Specific Instruction-Set Processors (ASIPs): Customized instruction sets for specific applications (e.g., DSPs).

Diagram Names

• Embedded System Architecture Diagram
• Microcontroller Block Diagram
• ASIP Design Flowchart

Common MCQ Areas

• Characteristics of embedded systems.
• Differences between general-purpose and single-purpose processors.
• ASIP design and optimization techniques.

Practice Tips

• Study “Embedded Systems Design” by Frank Vahid for embedded concepts.
• Analyze microcontroller datasheets (e.g., ATmega328) for architecture details.
• Design a simple embedded system (e.g., LED controller) on paper.
• Compare ASIPs with general-purpose processors for specific tasks.

Sample MCQs

1. An embedded system is characterized by:

   • a) General-purpose computing
   • b) Dedicated function
   • c) High power consumption
   • d) Large memory
   • Answer: b) Dedicated function.

2. ASIPs are optimized for:

   • a) General tasks
   • b) Specific applications
   • c) High cost
   • d) Slow performance
   • Answer: b) Specific applications.

4.5 Real-Time Operating and Control System (ACtE0405)

Key Concepts

Operating System Basics: Manages hardware, provides services (e.g., process management, memory allocation).

Task, Process, and Threads: Task (unit of work), process (program in execution), thread (lightweight process).

Multiprocessing and Multitasking: Multiple processes (multiprocessing) or tasks (multitasking) running concurrently.

Task Scheduling: Algorithms include FCFS, Round-Robin, Priority, Deadline-based (for real-time).

Task Synchronization: Prevents race conditions using semaphores, mutexes, monitors.

Device Drivers: Interface between OS and hardware (e.g., UART driver).

Open-Loop Control System: No feedback (e.g., timer-based irrigation).

Closed-Loop Control System: Uses feedback for accuracy (e.g., thermostat).

Diagram Names

• RTOS Task Scheduling Diagram
• Closed-Loop Control System Diagram
• Process State Transition Diagram

Common MCQ Areas

• Scheduling algorithms for real-time systems.
• Differences between open-loop and closed-loop control.
• Task synchronization mechanisms.

Practice Tips

• Study “Real-Time Systems” by Jane W.S. Liu for RTOS concepts.
• Practice scheduling tasks using Round-Robin and Priority algorithms.
• Design a closed-loop system (e.g., temperature controller) on paper.
• Study semaphore and mutex examples for synchronization.

Sample MCQs

1. A closed-loop control system uses:

   • a) No feedback
   • b) Feedback for control
   • c) Open-loop signals
   • d) Static inputs
   • Answer: b) Feedback for control.

2. Which scheduling algorithm is best for real-time systems?

   • a) FCFS
   • b) Round-Robin
   • c) Priority
   • d) Random
   • Answer: c) Priority.

4.6 Hardware Description Language and IC Technology (ACtE0406)

Key Concepts

VHDL Overview: Hardware Description Language for modeling digital systems (e.g., FPGA, ASIC design).

Overflow and Data Representation: Signed/unsigned numbers, overflow detection in VHDL (e.g., std_logic_vector).

Combinational Logic in VHDL: Models gates, MUX, adders (e.g., Y <= A AND B;).

Sequential Logic in VHDL: Models flip-flops, counters using processes (e.g., process(clk)).

Pipelining in VHDL: Implements pipeline stages for performance (e.g., registers between combinational logic).

Code Example

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity adder is
    port ( A, B : in STD_LOGIC; Sum, Carry : out STD_LOGIC );
end adder;
architecture Behavioral of adder is
begin
    Sum <= A XOR B;
    Carry <= A AND B;
end Behavioral;
  

Diagram Names

• VHDL Entity-Architecture Diagram
• Sequential Logic Process Diagram
• Pipelined Circuit Diagram

Common MCQ Areas

• VHDL syntax for combinational and sequential logic.
• Data types and overflow handling in VHDL.
• Pipelining benefits and implementation.

Practice Tips

• Study “VHDL for Digital Design” by Frank Vahid for VHDL basics.
• Write VHDL code for a 4-bit counter and full adder.
• Simulate VHDL designs using tools like ModelSim or Vivado.
• Design a pipelined adder in VHDL and analyze latency.

Sample MCQs

1. In VHDL, std_logic_vector is used for:

   • a) Single bit
   • b) Multiple bits
   • c) Integer
   • d) Boolean
   • Answer: b) Multiple bits.

2. Pipelining in VHDL improves:

   • a) Power consumption
   • b) Throughput
   • c) Memory size
   • d) Complexity
   • Answer: b) Throughput.

General Preparation Strategies

• Syllabus Review: Study the official NEC syllabus to focus on key topics.
• Textbooks: Use “Computer Organization and Architecture” by William Stallings for computer systems, “Embedded Systems Design” by Frank Vahid for embedded systems, and “VHDL for Digital Design” by Vahid for VHDL.
• Practice: Solve 20–30 MCQs per subtopic, focusing on numericals (e.g., cache hits, pipeline latency).
• Simulations: Use Logisim for digital circuits, ModelSim/Vivado for VHDL, and RTOS simulators for real-time systems.
• Time Management: Practice 10–15 MCQs in 12–15 minutes to match exam pace.

Conclusion

This comprehensive study guide covers all subtopics under 4. Computer Organization and Embedded System (ACtE04) for the NEC License Exam, providing detailed explanations, code examples, diagram names, and practice strategies. Designed as a reliable resource for students, it ensures thorough preparation for computer architecture, embedded systems, and hardware description languages. By mastering these topics and practicing MCQs, candidates can confidently excel in the exam.