2.Digital Logic, Combinational & Sequential Circuits, and Microprocessor Systems (AExE02)

2.1 Digital Logic

Number Systems and Conversions

Digital systems represent information using discrete values. Common number systems include Binary (base-2), Octal (base-8), Decimal (base-10), and Hexadecimal (base-16).

• Decimal (Base-10): Uses digits 0-9. Each position represents a power of 10.
• Binary (Base-2): Uses digits 0 and 1 (bits). Each position represents a power of 2.
• Octal (Base-8): Uses digits 0-7. Each position represents a power of 8.
• Hexadecimal (Base-16): Uses digits 0-9 and letters A-F (A=10, B=11, ..., F=15). Each position represents a power of 16.

Conversions:

Decimal to Other Bases: Repeated division by the base, collecting remainders from bottom up.

Example: Convert 25 (Decimal) to Binary

1. 25 / 2 = 12 remainder 1
2. 12 / 2 = 6 remainder 0
3. 6 / 2 = 3 remainder 0
4. 3 / 2 = 1 remainder 1
5. 1 / 2 = 0 remainder 1

Result: 11001_2

Other Bases to Decimal: Sum of (digit * base^position).

Example: Convert 11001_2 to Decimal

(1 * 2^4) + (1 * 2^3) + (0 * 2^2) + (0 * 2^1) + (1 * 2^0) = 16 + 8 + 0 + 0 + 1 = 25_10

Binary to Octal/Hexadecimal: Group binary digits. For Octal, group in 3s (from right). For Hex, group in 4s (from right).

Example: Convert 11010110_2 to Octal and Hexadecimal

• Octal: 011 010 110 -> 3 2 6_8
• Hexadecimal: 1101 0110 -> D 6_16

Logic Levels (HIGH/LOW, 0/1)

Digital circuits operate with two distinct voltage levels, typically referred to as HIGH and LOW. These levels represent binary states 1 and 0, respectively. In TTL (Transistor-Transistor Logic), HIGH usually corresponds to approximately +2V to +5V, and LOW to 0V to +0.8V. CMOS (Complementary Metal-Oxide-Semiconductor) logic uses near VCC for HIGH and near GND for LOW.

Logic Gates

Logic gates are the basic building blocks of any digital system. They perform fundamental logical operations based on their inputs.

AND Gate

Outputs HIGH (1) only if all inputs are HIGH (1).

Boolean Expression: Y = A AND B = A ⋅ B

A	B	Y
0	0	0
0	1	0
1	0	0
1	1	1

OR Gate

Outputs HIGH (1) if any input is HIGH (1).

Boolean Expression: Y = A OR B = A + B

A	B	Y
0	0	0
0	1	1
1	0	1
1	1	1

NOT Gate (Inverter)

Inverts the input signal. Outputs HIGH (1) if input is LOW (0), and vice versa.

Boolean Expression: Y = NOT A = A' or Ā

A	Y
0	1
1	0

NAND Gate

Outputs LOW (0) only if all inputs are HIGH (1). It's an AND gate followed by a NOT gate.

Boolean Expression: Y = (A ⋅ B)'

A	B	Y
0	0	1
0	1	1
1	0	1
1	1	0

NOR Gate

Outputs HIGH (1) only if all inputs are LOW (0). It's an OR gate followed by a NOT gate.

Boolean Expression: Y = (A + B)'

A	B	Y
0	0	1
0	1	0
1	0	0
1	1	0

XOR Gate (Exclusive OR)

Outputs HIGH (1) if an odd number of inputs are HIGH (1).

Boolean Expression: Y = A ⊕ B = A'B + AB'

A	B	Y
0	0	0
0	1	1
1	0	1
1	1	0

XNOR Gate (Exclusive NOR)

Outputs HIGH (1) if an even number of inputs are HIGH (1) (including zero HIGH inputs). It's an XOR gate followed by a NOT gate.

Boolean Expression: Y = (A ⊕ B)' = AB + A'B'

A	B	Y
0	0	1
0	1	0
1	0	0
1	1	1

Boolean Algebra Laws and Theorems

Boolean algebra provides a mathematical framework for analyzing and simplifying digital circuits.

• Commutative Laws:
  • A + B = B + A
  • A ⋅ B = B ⋅ A
• Associative Laws:
  • (A + B) + C = A + (B + C)
  • (A ⋅ B) ⋅ C = A ⋅ (B ⋅ C)
• Distributive Laws:
  • A ⋅ (B + C) = A ⋅ B + A ⋅ C
  • A + (B ⋅ C) = (A + B) ⋅ (A + C)
• Idempotent Laws:
  • A + A = A
  • A ⋅ A = A
• Identity Laws:
  • A + 0 = A
  • A ⋅ 1 = A
• Null (Dominance) Laws:
  • A + 1 = 1
  • A ⋅ 0 = 0
• Complementary Laws:
  • A + A' = 1
  • A ⋅ A' = 0
• Involution Law: (A')' = A
• Absorption Law:
  • A + A ⋅ B = A
  • A ⋅ (A + B) = A
  • A + A'B = A + B
• De Morgan's Theorems:
  • (A + B)' = A' ⋅ B'
  • (A ⋅ B)' = A' + B'

Sum-of-Products (SOP) Method

The SOP form expresses a Boolean function as a sum of product terms (minterms). A minterm is a product of all input variables, either in their true or complemented form, such that it evaluates to 1 for exactly one row of the truth table. The SOP expression is formed by ORing all minterms for which the function output is 1.

Example: Given a truth table:

A	B	F
0	0	0
0	1	1
1	0	1
1	1	0

The minterms where F=1 are A'B (for A=0, B=1) and AB' (for A=1, B=0).

SOP expression: F = A'B + AB' (which is an XOR gate).

Product-of-Sums (POS) Method

The POS form expresses a Boolean function as a product of sum terms (maxterms). A maxterm is a sum of all input variables, either in their true or complemented form, such that it evaluates to 0 for exactly one row of the truth table. The POS expression is formed by ANDing all maxterms for which the function output is 0.

Example: Using the same truth table:

A	B	F
0	0	0
0	1	1
1	0	1
1	1	0

The maxterms where F=0 are A+B (for A=0, B=0) and A'+B' (for A=1, B=1).

POS expression: F = (A+B)(A'+B') (which is an XNOR gate, the complement of XOR).

Truth Table to Karnaugh Map (K-map) Minimization

K-maps are a graphical method to simplify Boolean expressions. They visually represent a truth table and allow for easy identification of adjacent minterms (or maxterms) that can be combined to eliminate variables.

2-variable K-map

Structure: 2x2 grid. Each cell represents a minterm.

Example: F(A,B) = A'B + AB'

	B=0	B=1
A=0	0	1
A=1	1	0

No adjacent 1s can be grouped to simplify further than A'B + AB'.

3-variable K-map

Structure: 2x4 grid or 4x2 grid (Gray code ordering for variables). Cells are logically adjacent if they differ by only one bit.

Example: F(A,B,C) = Σm(0,1,2,3)

A\BC	00	01	11	10
0	1	1	1	1
1	0	0	0	0

Grouping the four 1s in the first row yields A'. So, F = A'.

4-variable K-map

Structure: 4x4 grid (Gray code ordering for both sets of variables).

Example: F(A,B,C,D) = Σm(0,2,5,7,8,10,13,15)

AB\CD	00	01	11	10
00	1	0	0	1
01	0	1	1	0
11	0	1	1	0
10	1	0	0	1

Grouping the corners (m0, m2, m8, m10) yields B'D'.

Grouping (m5, m7, m13, m15) yields BD.

Minimized expression: F = B'D' + BD = (B ⊕ D)' (XNOR).

Don't Care Conditions in K-maps

Don't care conditions ('X' or 'd') in a truth table represent output values that can be either 0 or 1 without affecting the circuit's operation. In K-maps, these 'X's can be grouped with 1s to form larger groups, leading to further simplification of the Boolean expression. They are treated as 1s if they help simplify and as 0s otherwise.

Example: F(A,B,C) = Σm(0,1,5) + Σd(2,3)

A\BC	00	01	11	10
0	1	1	X	X
1	0	1	0	0

Grouping (m0, m1, d2, d3) yields A'.

Grouping (m1, m5) yields B'C.

The minimal solution would be F = A' + B'C.

2.2 Combinational and Arithmetic Circuits

Multiplexers (MUX)

A multiplexer (MUX) is a data selector. It takes multiple input lines and routes one of them to a single output line based on the value of select lines.

• 2:1 MUX: 2 data inputs (I0, I1), 1 select line (S), 1 output (Y).

  Boolean Expression: Y = S'I0 + SI1

• 4:1 MUX: 4 data inputs, 2 select lines.

  Boolean Expression: Y = S1'S0'I0 + S1'S0I1 + S1S0'I2 + S1S0I3

• 8:1 MUX: 8 data inputs, 3 select lines.

Boolean expression implementation: Any Boolean function of 'n' variables can be implemented using a (2^n):1 MUX, or more efficiently with a (2^(n-1)):1 MUX where one variable is used as a data input to the MUX.

Demultiplexers (DEMUX)

A demultiplexer (DEMUX) performs the reverse operation of a MUX. It takes a single input data line and routes it to one of multiple output lines based on the value of select lines.

• 1:2 DEMUX: 1 data input (D), 1 select line (S), 2 outputs (Y0, Y1).

  Boolean Expressions: Y0 = S'D, Y1 = SD

• 1:4 DEMUX: 1 data input, 2 select lines.
• 1:8 DEMUX: 1 data input, 3 select lines.

Decoder

A decoder converts binary information from N input lines to a maximum of 2^N unique output lines. Only one output line is active at any given time, corresponding to the binary code on the input lines.

• Binary to Decimal Decoder (e.g., 2-to-4 Decoder): Converts a 2-bit binary input to one of four unique outputs (00 -> Y0, 01 -> Y1, etc.).
• BCD to 7-segment Decoder: Takes a 4-bit BCD (Binary-Coded Decimal) input and outputs control signals for a 7-segment display to show the corresponding decimal digit (0-9). Each output line (a, b, c, d, e, f, g) controls one segment.

Encoder

An encoder performs the inverse operation of a decoder. It converts an active input signal into a coded output (e.g., binary, BCD).

• Priority Encoder: If multiple inputs are active, the output corresponds to the input with the highest priority. For example, in an 8-to-3 priority encoder, if both input 3 and input 5 are active, the output will be 101 (binary for 5), as input 5 has higher priority.

Binary Addition

Digital circuits perform arithmetic operations using logic gates.

• Half Adder: Adds two single binary digits (A, B) and produces a Sum (S) and a Carry (C_out).

  Truth Table:

  A	B	S	C_out
  0	0	0	0
  0	1	1	0
  1	0	1	0
  1	1	0	1

  Boolean Expressions: S = A ⊕ B, C_out = A ⋅ B

  Circuit Description: Implemented with one XOR gate for Sum and one AND gate for Carry.

• Full Adder: Adds three single binary digits (A, B, C_in - input carry) and produces a Sum (S) and a Carry (C_out).

  Truth Table:

  A	B	C_in	S	C_out
  0	0	0	0	0
  0	0	1	1	0
  0	1	0	1	0
  0	1	1	0	1
  1	0	0	1	0
  1	0	1	0	1
  1	1	0	0	1
  1	1	1	1	1

  Boolean Expressions: S = A ⊕ B ⊕ C_in, C_out = AB + BC_in + AC_in

  Circuit Description: Can be implemented using two half adders and one OR gate.

Binary Subtraction

Similar to addition, subtraction can be implemented using half and full subtractors.

• Half Subtractor: Subtracts one single binary digit (B) from another (A) and produces a Difference (D) and a Borrow (B_out).

  Boolean Expressions: D = A ⊕ B, B_out = A'B

• Full Subtractor: Subtracts three single binary digits (A, B, B_in - input borrow) and produces a Difference (D) and a Borrow (B_out).

  Boolean Expressions: D = A ⊕ B ⊕ B_in, B_out = A'B + A'B_in + BB_in

Operations on Unsigned and Signed Binary Numbers

• Unsigned Numbers: All bits represent the magnitude. An N-bit number can represent values from 0 to (2^N)-1.
• Signed Numbers: Various methods to represent positive and negative numbers.
  • Sign-Magnitude: The most significant bit (MSB) indicates the sign (0 for positive, 1 for negative), and the remaining bits represent the magnitude.

    Example (4-bit): 0101 = +5, 1101 = -5. Has issues with two representations for zero (+0 and -0).

  • 1's Complement: To find the 1's complement of a binary number, invert all its bits (0 becomes 1, 1 becomes 0).

    Example (4-bit): +5 is 0101. -5 in 1's complement is 1010. Still has two zeros.

  • 2's Complement: The most widely used method for signed integer representation. To find the 2's complement, take the 1's complement and add 1.

    Example (4-bit): +5 is 0101. 1's complement of +5 is 1010. Adding 1 gives 1011, which is -5 in 2's complement. This method has a unique representation for zero and simplifies arithmetic operations (subtraction becomes addition of a negative number).

2.3 Sequential Logic Circuits

Sequential circuits are digital circuits whose outputs depend not only on the present inputs but also on the sequence of past inputs, meaning they have memory. Flip-flops are the fundamental memory elements.

RS Flip-Flop

The RS (Reset-Set) flip-flop is a basic latch, typically built from two cross-coupled NOR or NAND gates.

• Truth Table (Characteristic Table):

  S	R	Q(t+1)	Comment
  0	0	Q(t)	No Change (Memory)
  0	1	0	Reset
  1	0	1	Set
  1	1	Invalid	Forbidden State

• Characteristic Equation: Q(t+1) = S + R'Q(t) (for NOR-based latch, S=1, R=0 is Set; S=0, R=1 is Reset; S=1, R=1 is invalid)
• Timing Diagram: Shows how the output Q changes in response to S and R inputs over time. The output changes asynchronously with inputs.
• Circuit Description: Two NOR gates where the output of each gate is connected to an input of the other gate, and S and R are the other inputs.

Gated Flip-Flops

Gated flip-flops add an enable (EN) or clock (CLK) input, allowing the flip-flop to change state only when the enable signal is active.

• Gated SR Flip-Flop: Behaves like an SR latch when EN is HIGH. When EN is LOW, the state holds.
• Gated D Flip-Flop: A D (Data) flip-flop overcomes the invalid state of the SR flip-flop. When EN is HIGH, the output Q follows the input D. When EN is LOW, the output holds its current state.

  Characteristic Equation: Q(t+1) = D (when enabled)

Edge-Triggered Flip-Flops

Edge-triggered flip-flops change state only at the rising or falling edge of the clock signal, making them synchronous. This prevents race conditions and allows for precise timing control.

• Positive Edge-Triggered: Changes state only on the rising edge (LOW to HIGH transition) of the clock pulse.
• Negative Edge-Triggered: Changes state only on the falling edge (HIGH to LOW transition) of the clock pulse.

Master-Slave Flip-Flops

A master-slave flip-flop consists of two cascaded latches (a master and a slave) controlled by opposite phases of a clock signal. The master latches the input on one clock edge, and the slave copies the master's state on the opposite clock edge. This design prevents "race-around" conditions where the output changes multiple times within a single clock pulse.

Types of Registers

A register is a group of flip-flops used to store multiple bits of binary data.

• Shift Register: A register capable of shifting its stored bits to the left or right. Used for serial data transfer, serial-to-parallel conversion, and vice versa.
  • Serial-In, Serial-Out (SISO)
  • Serial-In, Parallel-Out (SIPO)
  • Parallel-In, Serial-Out (PISO)
  • Parallel-In, Parallel-Out (PIPO)
• Parallel Register: A register where all bits are loaded or output simultaneously (in parallel).

Applications of Shift Registers

• Serial-to-Parallel Conversion: Serial data is shifted in bit by bit and then read out all at once in parallel.
• Parallel-to-Serial Conversion: Parallel data is loaded simultaneously into the register and then shifted out one bit at a time.
• Data manipulation, sequence generation, frequency division.

Asynchronous Counters (Ripple Counters)

In asynchronous counters, the output of one flip-flop serves as the clock input for the next flip-flop. This creates a "ripple" effect as the clock signal propagates through the chain.

• Ripple Counter: Simple to design, but propagation delays accumulate, limiting speed and causing glitches. A 4-bit ripple counter will count from 0 to 15.
• Mod-N Counters: A counter that counts up to N-1 and then resets. Can be designed by adding feedback logic (e.g., a NAND gate) to clear the flip-flops when a specific count is reached.

Synchronous Counters

In synchronous counters, all flip-flops are clocked simultaneously by a common clock signal. Logic gates determine the next state based on the current state, ensuring faster and more reliable operation compared to asynchronous counters.

• Synchronous Up/Down Counter: Can count in both ascending and descending sequences, controlled by an up/down control input.
• Design Procedure:
  1. State Diagram: Define the desired sequence of states.
  2. State Table: List present states, next states, and outputs.
  3. Flip-flop Excitation Table: Determine the required inputs for each flip-flop to transition from present to next state.
  4. K-maps: Simplify the flip-flop input equations.
  5. Logic Implementation: Draw the circuit using flip-flops and logic gates.

2.4 Microprocessor

A microprocessor is a computer processor where the data processing logic and control are included on a single integrated circuit (IC).

Internal Architecture of Microprocessor

• Registers: Small, high-speed storage locations within the CPU.
  • General Purpose Registers: Used by programmers for temporary data storage during computations.
  • Special Purpose Registers: Program Counter (PC - stores address of next instruction), Stack Pointer (SP - points to top of stack), Instruction Register (IR - holds current instruction), Memory Address Register (MAR), Memory Data Register (MDR), Status/Flag Register (stores results of operations like carry, zero, sign).
• Arithmetic Logic Unit (ALU): Performs arithmetic operations (addition, subtraction, multiplication, division) and logical operations (AND, OR, NOT, XOR).
• Control Unit (CU): Directs and coordinates most of the operations carried out by the CPU. It fetches instructions, decodes them, and generates control signals to execute them.
• Buses: Collections of wires used for communication between different components of the microprocessor and external devices.
  • Data Bus: Carries data between the CPU, memory, and I/O devices. Its width determines how many bits can be transferred at once.
  • Address Bus: Carries memory addresses from the CPU to memory and I/O devices. Its width determines the maximum memory capacity the CPU can address.
  • Control Bus: Carries control signals (e.g., read/write, memory request, I/O request, interrupt acknowledge) from the CPU to other components.

Features of Microprocessor

• Data Bus Width: The number of bits the CPU can process or transfer in a single operation (e.g., 8-bit, 16-bit, 32-bit, 64-bit). Wider buses generally lead to higher performance.
• Clock Speed: Measured in MHz or GHz, it indicates how many instruction cycles the CPU can perform per second. Higher clock speed generally means faster processing.
• Instruction Set: The complete set of commands (instructions) that a particular CPU can understand and execute. Can be Complex Instruction Set Computer (CISC) or Reduced Instruction Set Computer (RISC).

Assembly Language Programming

Assembly language is a low-level programming language that has a strong correspondence between the language and the architecture's machine code instructions. It uses mnemonic codes for instructions.

• Instructions:
  • MOV destination, source: Move data from source to destination.

    Example: MOV AX, 1234H (Move hexadecimal value 1234 to AX register).

  • ADD destination, source: Add source to destination.

    Example: ADD BX, CX (Add content of CX to BX, store in BX).

  • SUB destination, source: Subtract source from destination.

    Example: SUB AX, 05H (Subtract 5 from AX).

  • JMP label: Unconditional jump to a specified label (address).
  • CALL subroutine_address: Call a subroutine. Pushes the return address onto the stack.
  • RET: Return from a subroutine. Pops the return address from the stack and jumps to it.

Addressing Modes

Addressing modes specify how the operand of an instruction is located. They define the rule for calculating the effective address of an operand.

• Immediate Addressing: The operand value is directly specified in the instruction.

  Example: MOV AX, 5000H (5000H is the operand).

• Direct Addressing: The instruction contains the direct memory address of the operand.

  Example: MOV AX, [2000H] (Move content of memory location 2000H to AX).

• Register Addressing: The operand is stored in a CPU register.

  Example: MOV AX, BX (Move content of BX register to AX).

• Register Indirect Addressing: The instruction specifies a register that contains the address of the operand.

  Example: MOV AX, [BX] (Move content of memory location pointed to by BX to AX).

• Indexed Addressing: The effective address is calculated by adding a base address (from an instruction or register) to an index value (from an index register). Useful for accessing array elements.

  Example: MOV AX, [BX + SI]

• Relative Addressing: The effective address is calculated by adding an offset (specified in the instruction) to the current value of the Program Counter (PC). Used for position-independent code and jumps.

2.5 Microprocessor System

A microprocessor system integrates the microprocessor with memory, input/output (I/O) devices, and other peripheral components.

Memory Device Classification

• RAM (Random Access Memory): Volatile memory, data is lost when power is off.
  • SRAM (Static RAM): Faster, uses latches, more expensive, used for cache.
  • DRAM (Dynamic RAM): Slower, uses capacitors, needs refreshing, cheaper, used for main memory.
• ROM (Read-Only Memory): Non-volatile memory, data persists without power.
  • PROM (Programmable ROM): Programmed once by the user.
  • EPROM (Erasable PROM): Erasable by UV light, reprogrammable.
  • EEPROM (Electrically Erasable PROM): Erasable and reprogrammable electrically, byte by byte.
  • Flash Memory: A type of EEPROM, electrically erasable in blocks, widely used in SSDs, USB drives.

Memory Hierarchy

A tiered structure of memory components, organized by speed, cost, and capacity.

1. Registers: Smallest, fastest, most expensive (inside CPU).
2. Cache Memory (L1, L2, L3): Small, fast SRAM, stores frequently accessed data/instructions (close to CPU).
3. Main Memory (RAM): Larger, slower DRAM (system RAM).
4. Secondary Storage: Largest, slowest, cheapest (HDDs, SSDs, optical drives).

The goal is to provide fast access to data while keeping costs low, by exploiting locality of reference.

Interfacing I/O and Memory

Microprocessors communicate with I/O devices and memory via buses. There are two primary methods for organizing this communication:

• Memory-Mapped I/O: I/O devices are treated as memory locations. The CPU uses the same instructions (e.g., MOV) to access both memory and I/O devices. This simplifies the instruction set but reduces the available memory address space.
• I/O Mapped I/O (Port-Mapped I/O): I/O devices have a separate address space from memory. The CPU uses special I/O instructions (e.g., IN, OUT) to access I/O ports. This preserves the full memory address space but requires dedicated I/O instructions.

Parallel Interface (8255 PPI)

A Programmable Peripheral Interface (PPI) is a general-purpose I/O chip that allows the microprocessor to communicate with peripheral devices in parallel.

• 8255 PPI: A widely used Intel PPI chip. It has three 8-bit parallel ports (Port A, Port B, Port C) that can be configured as input or output.

  Modes of Operation:

  • Mode 0 (Basic I/O): Simple input/output without handshaking. Ports A, B, and C can be configured as 8-bit input or output ports.
  • Mode 1 (Strobed I/O): Provides handshaking signals for data transfer. Port A and Port B can be configured for strobed input or output. Port C bits are used for handshaking.
  • Mode 2 (Bi-directional Strobed I/O): Allows Port A to be configured for bi-directional data transfer with handshaking. Port C bits are used for handshaking, and Port B can operate in Mode 0 or Mode 1.

Serial Interface (UART, USART)

Serial communication transmits data one bit at a time over a single channel.

• UART (Universal Asynchronous Receiver/Transmitter): A chip or circuit block that handles asynchronous serial communication. It converts parallel data from the CPU into serial data for transmission and converts incoming serial data into parallel data for the CPU.
• USART (Universal Synchronous/Asynchronous Receiver/Transmitter): More versatile than a UART, as it supports both asynchronous and synchronous serial communication.

Synchronous and Asynchronous Transmission

• Asynchronous Transmission: Data is sent in frames (bytes) with start and stop bits. No common clock signal is shared between sender and receiver. Timing is derived from the data itself.
• Synchronous Transmission: Data is sent in continuous blocks (frames) synchronized by a shared clock signal. More efficient for large data transfers as it doesn't require start/stop bits for each byte.

Serial Interface Standards

• RS-232: A standard for serial communication commonly used for connecting DTE (Data Terminal Equipment) to DCE (Data Communication Equipment). It defines voltage levels, signaling rates, and pin assignments for point-to-point communication. Uses single-ended signaling.
• RS-485: A standard for serial communication that allows for multi-drop configurations (multiple devices on a single bus) and uses differential signaling, making it more robust against noise and suitable for longer distances.

Direct Memory Access (DMA) and DMA Controllers (8257)

• Direct Memory Access (DMA): A feature that allows certain hardware subsystems in a computer to access main system memory (RAM) independently of the central processing unit (CPU). This is crucial for high-speed I/O devices (e.g., disk controllers, network cards) to transfer data directly to/from memory without constantly involving the CPU, thus freeing up the CPU for other tasks.
• DMA Controllers (8257): A dedicated chip that manages DMA operations. When an I/O device needs to transfer data via DMA, it signals the DMA controller, which then requests control of the buses from the CPU. Once granted, the DMA controller manages the data transfer between the I/O device and memory directly, without CPU intervention.

2.6 Interrupt Operations

Interrupts are signals that temporarily halt the CPU's current execution to handle an urgent event or request. This allows the CPU to respond to external events efficiently.

Interrupt Types

• Hardware Interrupts: Generated by external hardware devices (e.g., keyboard press, timer overflow, I/O device completion). They are signaled via dedicated interrupt lines to the CPU.
• Software Interrupts: Generated by an instruction within a program (e.g., INT n instruction in x86 architecture) or by exceptional conditions (e.g., division by zero, page fault).
• Maskable Interrupts: Interrupts that can be enabled or disabled (masked) by the CPU through software control (e.g., by setting/clearing bits in the flag register). Most I/O device interrupts are maskable.
• Non-Maskable Interrupts (NMI): High-priority interrupts that cannot be disabled by the CPU. They are typically reserved for critical system errors (e.g., memory parity error, power failure).

Interrupt Service Routine (ISR)

An Interrupt Service Routine (ISR), also known as an interrupt handler, is a special software routine executed by the CPU in response to an interrupt. It contains the code necessary to handle the specific event that caused the interrupt.

Interrupt Processing

When an interrupt occurs, the CPU undergoes a sequence of steps to handle it:

1. Save Context: The CPU completes its current instruction, saves the current state (Program Counter, status flags, and sometimes other registers) onto the stack.
2. Interrupt Acknowledge: The CPU sends an interrupt acknowledge signal to the interrupting device or interrupt controller.
3. Interrupt Vector: The interrupting device or controller provides an "interrupt vector" (a number) to the CPU. This vector is an index into a table (Interrupt Vector Table) that contains the starting addresses of the corresponding ISRs.
4. Load ISR Address: The CPU loads the address of the appropriate ISR from the Interrupt Vector Table into the Program Counter.
5. Execute ISR: The CPU begins executing the Interrupt Service Routine.
6. Restore Context: After the ISR completes, the CPU restores the saved context from the stack.
7. Return to Main Program: The CPU resumes execution of the interrupted program from where it left off.

Interrupt Priority: When multiple interrupts occur simultaneously, an interrupt controller (e.g., 8259A PIC) manages their priority. Higher-priority interrupts are handled before lower-priority ones.