Comprehensive Study Guide for NEC License Exam - Computer Engineering

2. Digital Logic and Microprocessor (AExE02)

Introduction

The Nepal Engineering Council (NEC) License Exam is a mandatory requirement for Computer Engineering graduates in Nepal to register as professional engineers. The section 2. Digital Logic and Microprocessor (AExE02) tests foundational knowledge in digital circuits and microprocessor systems, essential for applications like hardware design, embedded systems, and processor interfacing. This comprehensive note covers all subtopics (2.1 to 2.6) with detailed explanations, formulas, diagram names, and exam-focused strategies to ensure students can rely on it for thorough preparation. The exam consists of 100 multiple-choice questions (MCQs), with 10 marks allocated to this section, requiring a 50% passing threshold and no negative marking.

The syllabus includes:

2.1 Digital logic (AExE0201)
2.2 Combinational and arithmetic circuits (AExE0202)
2.3 Sequential logic circuit (AExE0203)
2.4 Microprocessor (AExE0204)
2.5 Microprocessor system (AExE0205)
2.6 Interrupt operations (AExE0206)

2.1 Digital Logic (AExE0201)

Key Concepts

Number Systems: Digital systems use various number systems to represent data:

Binary (base-2): Uses 0 and 1 (e.g., 1011₂ = 1 × 2³ + 0 × 2² + 1 × 2¹ + 1 × 2⁰ = 11₁₀).
Decimal (base-10): Standard counting system (0–9).
Octal (base-8): Uses 0–7 (e.g., 17₈ = 1 × 8¹ + 7 × 8⁰ = 15₁₀).
Hexadecimal (base-16): Uses 0–9, A–F (e.g., 1A₁₆ = 1 × 16¹ + 10 × 16⁰ = 26₁₀).
Conversions: Binary to decimal, decimal to binary, binary to hex, etc.

Logic Levels: Represent binary states:

High (1): Typically 5V or 3.3V in TTL/CMOS circuits.
Low (0): Typically 0V.
Noise Margins: Difference between output and input voltage levels to ensure reliable operation (e.g., V_OH - V_IH for high state).

Logic Gates: Building blocks of digital circuits:

Basic Gates: AND (Y = A ċ B), OR (Y = A + B), NOT (Y = A’).
Universal Gates: NAND, NOR (can implement any logic function).
Other Gates: XOR (Y = A ⊕ B), XNOR.
Truth Tables: Define gate behavior (e.g., AND: 1 only if all inputs are 1).

Boolean Algebra: Simplifies logic expressions:

Laws: Commutative (A + B = B + A), Associative, Distributive (A(B + C) = AB + AC).
De Morgan’s Theorems: (A + B)’ = A’ ċ B’, (A ċ B)’ = A’ + B’.
Simplification: E.g., A + A’ = 1, A ċ A’ = 0.

Sum-of-Products (SOP): Expresses function as sum of minterms (e.g., F = AB + A’C).

Product-of-Sums (POS): Expresses function as product of maxterms (e.g., F = (A + B)(A’ + C)).

Truth Table to Karnaugh Map (K-Map): Simplifies Boolean expressions by grouping 1s (minterms) or 0s (maxterms) in a grid (e.g., 3-variable K-Map reduces terms by grouping adjacent 1s).

Important Formulas

Binary to Decimal: ∑(d_i ċ 2ⁱ), where d_i is the binary digit.
De Morgan’s: (A + B)’ = A’ ċ B’, (A ċ B)’ = A’ + B’.
K-Map: Group 2ⁿ cells to minimize terms.

Diagram Names

Logic Gates Diagram
3-Variable K-Map Diagram
Truth Table Diagram

Common MCQ Areas

Converting between binary, decimal, octal, and hexadecimal.
Truth tables and Boolean expression simplification for logic gates.
Minimizing expressions using K-Maps for SOP and POS forms.

Practice Tips

Study “Digital Design” by Morris Mano for number systems, gates, and Boolean algebra.
Practice conversions (e.g., binary to hex) and simplify expressions using Boolean laws.
Create K-Maps for 3- and 4-variable functions to derive SOP/POS expressions.
Simulate logic gates using software like Logisim to visualize truth tables.

Sample MCQs

Convert 2B₁₆ to binary:
- a) 101011
- b) 00101011
- c) 101100
- d) 110010
- Answer: b) 00101011 (2 = 0010, B = 1011).
Simplify F = AB + AB’ using Boolean algebra:
- a) A
- b) B
- c) A + B
- d) AB
- Answer: a) A (F = A(B + B’) = A ċ 1 = A).

2.2 Combinational and Arithmetic Circuits (AExE0202)

Key Concepts

Multiplexers (MUX): Selects one input from multiple inputs based on select lines (e.g., 4:1 MUX selects 1 of 4 inputs using 2 select lines).

Demultiplexers (DEMUX): Routes one input to multiple outputs (e.g., 1:4 DEMUX routes to 1 of 4 outputs).

Decoder: Converts binary input to one-hot output (e.g., 2-to-4 decoder activates one of 4 outputs).

Encoder: Converts one-hot input to binary output (e.g., 4-to-2 encoder).

Binary Addition:

Half Adder: S = A ⊕ B, C = A ċ B.
Full Adder: S = A ⊕ B ⊕ C_in, C_out = (A ċ B) + (B ċ C_in) + (A ċ C_in).

Binary Subtraction: Uses 2’s complement: A - B = A + (-B), where -B = invert(B) + 1.

Unsigned/Signed Binary Operations: Unsigned uses direct addition/subtraction; signed uses 2’s complement for negative numbers.

Important Formulas

MUX Outputs: 2ⁿ inputs for n select lines.
Full Adder: S = A ⊕ B ⊕ C_in, C_out = AB + BC_in + AC_in.
2’s Complement: -X = invert(X) + 1.

Diagram Names

4:1 Multiplexer Diagram
2-to-4 Decoder Diagram
Full Adder Circuit Diagram

Common MCQ Areas

Functionality and truth tables of MUX, DEMUX, decoders, and encoders.
Outputs of half and full adders for given inputs.
2’s complement arithmetic for signed numbers.

Practice Tips

Study “Digital Logic and Computer Design” by Morris Mano for combinational circuits.
Practice designing MUX/DEMUX circuits and adders/subtractors.
Perform 2’s complement calculations for 4-bit and 8-bit numbers.
Simulate circuits using Logisim to verify truth tables and outputs.

Sample MCQs

For a full adder with A = 0, B = 1, C_in = 1, the sum and carry are:
- a) S = 0, C_out = 0
- b) S = 0, C_out = 1
- c) S = 1, C_out = 0
- d) S = 1, C_out = 1
- Answer: b) S = 0, C_out = 1 (S = 0 ⊕ 1 ⊕ 1 = 0, C_out = (0 ċ 1) + (1 ċ 1) + (0 ċ 1) = 1).
A 4:1 MUX with select lines S1S0 = 10 selects:
- a) Input I0
- b) Input I1
- c) Input I2
- d) Input I3
- Answer: c) Input I2 (S1S0 = 10₂ = 2₁₀ selects I2).

2.3 Sequential Logic Circuit (AExE0203)

Key Concepts

RS Flip-Flops: Basic memory element with Set (S) and Reset (R) inputs; outputs Q, Q’. Forbidden state: S = R = 1.

Gated Flip-Flops: Include enable input (e.g., clock) to control state changes, preventing unwanted transitions.

Edge-Triggered Flip-Flops: Change state on clock edge (rising/falling):

D Flip-Flop: Output follows input D on clock edge.
JK Flip-Flop: Versatile, supports set, reset, hold, toggle.
T Flip-Flop: Toggles output when T = 1.

Master-Slave Flip-Flops: Two-stage flip-flops to avoid race conditions in high-speed circuits.

Registers: Store multiple bits (e.g., 4-bit register). Types: Shift, parallel-in/parallel-out, serial-in/serial-out.

Shift Registers: Shift data left/right. Applications: Data storage, serial-to-parallel conversion, delay lines.

Asynchronous Counters: Ripple counters; each flip-flop triggered by previous stage, slower due to propagation delay.

Synchronous Counters: All flip-flops triggered by same clock, faster and synchronized.

Important Formulas

JK Flip-Flop: Q_next = J ċ Q’ + K’ ċ Q.
Counter Modulus: Mod = 2ⁿ, where n is number of flip-flops.

Diagram Names

RS Flip-Flop Diagram
D Flip-Flop Diagram
4-Bit Shift Register Diagram
3-Bit Synchronous Counter Diagram

Common MCQ Areas

Truth tables and state transitions for flip-flops (RS, D, JK, T).
Shift register applications and data shifting.
Counter design, including modulus and sequence (e.g., mod-8 counter).

Practice Tips

Study “Digital Design” by Morris Mano for sequential circuits and counters.
Practice state tables for JK and D flip-flops with given inputs.
Design mod-4 and mod-8 counters, both synchronous and asynchronous.
Simulate shift registers and counters using Logisim or Vivado.

Sample MCQs

For a D flip-flop with D = 1, current Q = 0, next state Q_next is:
- a) 0
- b) 1
- c) Toggle
- d) Invalid
- Answer: b) 1 (Q_next = D = 1).
A 3-bit synchronous counter counts from 000 to:
- a) 111
- b) 110
- c) 101
- d) 100
- Answer: a) 111 (Mod = 2³ = 8, counts 000 to 111).

2.4 Microprocessor (AExE0204)

Key Concepts

Internal Architecture: Key components of a microprocessor (e.g., 8085):

ALU: Performs arithmetic and logical operations.
Registers: Accumulator, B, C, D, E, H, L (8-bit in 8085).
Control Unit: Directs operations using instruction decoder.
Program Counter (PC): Holds address of next instruction.
Stack Pointer (SP): Manages stack for subroutine calls.
Buses: 8-bit data bus, 16-bit address bus in 8085.

Features: 8085 supports 74 instructions, 5 interrupts, 5 MHz clock, addressing modes (immediate, register, direct, indirect).

Assembly Language Programming: Uses mnemonics for low-level coding:

Instructions: MOV A, B (move data), ADD B (add to accumulator), JMP (jump).
Addressing Modes: Immediate (e.g., MVI A, 05H), register, direct, indirect.

Important Formulas

Instruction Cycle Time: T = 1 / (clock frequency) (e.g., 5 MHz → T = 0.2 μs).
Memory Addressing: Total addresses = 2ⁿ, where n is address bus width (e.g., 16-bit → 64 KB).

Diagram Names

8085 Microprocessor Architecture Diagram
Instruction Cycle Diagram
Assembly Code Flowchart

Common MCQ Areas

Components of 8085 architecture and their functions.
Instruction types and addressing modes (e.g., immediate vs. direct).
Predicting outputs of simple assembly programs.

Practice Tips

Study “Microprocessor Architecture, Programming, and Applications” by Ramesh Gaonkar for 8085 details.
Write assembly programs for tasks like addition, looping, and branching.
Understand instruction cycle: fetch, decode, execute.
Simulate 8085 programs using tools like GNUSim8085.

Sample MCQs

In 8085, the instruction ADI 05H performs:
- a) Move 05H to accumulator
- b) Add 05H to accumulator
- c) Subtract 05H from accumulator
- d) Compare 05H with accumulator
- Answer: b) Add 05H to accumulator.
The 8085 address bus width allows addressing:
- a) 16 KB
- b) 32 KB
- c) 64 KB
- d) 128 KB
- Answer: c) 64 KB (2¹⁶ = 64 KB).

2.5 Microprocessor System (AExE0205)

Key Concepts

Memory Device Classification and Hierarchy:

RAM: SRAM (fast, used in cache), DRAM (main memory).
ROM: PROM, EPROM, EEPROM (non-volatile storage).
Hierarchy: Registers (fastest), cache, main memory, secondary storage (slowest).

Interfacing I/O and Memory:

Parallel Interface: Transfers multiple bits simultaneously (e.g., 8255 PPI with Ports A, B, C).
Programmable Peripheral Interface (PPI): 8255 modes: Mode 0 (basic I/O), Mode 1 (strobed I/O), Mode 2 (bidirectional).

Serial Interface:

Synchronous: Uses clock (e.g., SPI, I2C).
Asynchronous: Uses start/stop bits (e.g., UART).
Standards: RS-232 (serial port), USB, I2C (inter-chip communication).

Direct Memory Access (DMA): Transfers data between memory and I/O without CPU intervention, using controllers like 8237.

Important Formulas

Memory Size: Size = 2ⁿ ċ word length, where n is address lines.
Baud Rate: Baud rate = Clock frequency / Divisor (for UART).

Diagram Names

Memory Hierarchy Diagram
8255 PPI Block Diagram
UART Serial Interface Diagram
DMA Controller Diagram

Common MCQ Areas

Memory types (RAM vs. ROM) and hierarchy characteristics.
8255 PPI modes and port configurations.
Differences between serial (synchronous/asynchronous) and parallel interfaces.
DMA operation and controller functions.

Practice Tips

Study “Microprocessor Architecture, Programming, and Applications” by Gaonkar for interfacing and DMA.
Practice configuring 8255 PPI for different modes.
Compare synchronous (SPI) and asynchronous (UART) data transfer.
Simulate memory and I/O interfacing using 8085/8086 emulators.

Sample MCQs

The 8255 PPI in Mode 0 is used for:
- a) Basic I/O
- b) Strobed I/O
- c) Bidirectional I/O
- d) Interrupt-driven I/O
- Answer: a) Basic I/O.
A microprocessor with 10 address lines can address:
- a) 1 KB
- b) 2 KB
- c) 4 KB
- d) 8 KB
- Answer: a) 1 KB (2¹⁰ = 1024 bytes = 1 KB).

2.6 Interrupt Operations (AExE0206)

Key Concepts

Interrupt: Signal to pause CPU for urgent tasks:

Hardware Interrupts: Triggered by external devices (e.g., 8085: TRAP, RST 7.5).
Software Interrupts: Triggered by program instructions (e.g., 8085: RST 0–7).

Interrupt Service Routine (ISR): Code executed in response to an interrupt, stored at specific memory addresses (e.g., 8085 RST 7.5 at 003CH).

Interrupt Processing: Steps include saving current state (registers, PC), executing ISR, and restoring state. 8085 supports 5 interrupts with priority: TRAP (highest), RST 7.5, 6.5, 5.5, INTR.

Important Formulas

Interrupt Latency: Time from interrupt request to ISR execution start.
Vector Address (8085): Address = Vector number ċ 8 (e.g., RST 6.5 → 6.5 ċ 8 = 0034H).

Diagram Names

Interrupt Processing Flowchart
8085 Interrupt Vector Table Diagram
Interrupt Priority Diagram

Common MCQ Areas

Types and priorities of 8085 interrupts.
Steps in interrupt service routine execution.
Calculating interrupt vector addresses.

Practice Tips

Study “Microprocessor Architecture, Programming, and Applications” by Gaonkar for interrupt mechanisms.
Practice calculating vector addresses for 8085 interrupts (e.g., RST 5.5, 6.5).
Write ISRs for simple interrupt tasks (e.g., I/O handling).
Simulate interrupt handling using 8085 emulators like GNUSim8085.

Sample MCQs

In 8085, the highest priority interrupt is:
- a) RST 7.5
- b) TRAP
- c) INTR
- d) RST 5.5
- Answer: b) TRAP (non-maskable, highest priority).
The vector address for 8085 RST 5.5 is:
- a) 002CH
- b) 0034H
- c) 0024H
- d) 003CH
- Answer: a) 002CH (5.5 ċ 8 = 44₁₀ = 002CH).

General Preparation Strategies

Syllabus Review: Refer to the official NEC syllabus to focus on key areas.
Textbooks: Study “Digital Design” by Morris Mano for digital logic and “Microprocessor Architecture, Programming, and Applications” by Ramesh Gaonkar for microprocessor systems.
Practice: Solve 20–30 MCQs per subtopic, focusing on numericals (e.g., K-Maps, adders, vector addresses).
Simulations: Use Logisim for digital circuits and GNUSim8085 for microprocessor programs to visualize concepts.
Time Management: Practice 10–15 MCQs in 12–15 minutes to match exam pace.

Conclusion

This comprehensive study guide covers all subtopics under 2. Digital Logic and Microprocessor (AExE02) for the NEC License Exam, providing detailed explanations, formulas, diagram names, and practice strategies. Designed as a reliable resource for students, it ensures thorough preparation for digital circuits and microprocessor systems. By mastering these concepts and practicing MCQs, candidates can confidently excel in the exam.